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Arteris, Inc. explores multi die design to improve NoC topology and data movement
Arteris, Inc. published insights from Ashley Stevens on the pivotal role of topology and data movement in multi die design.
In his recent article for Design & Reuse, Stevens examines how Network on Chip (NoC) topology shapes latency, bandwidth, and coherency across increasingly complex architectures. The discussion delves into practical approaches for optimizing data transfers and performance at scale, reflecting ongoing innovation in the semiconductor industry.
Arteris, Inc. recently announced that interconnect, rather than processing power, has become the key constraint for semiconductor performance and scalability, according to a company statement published earlier this year. The firm has also partnered with Renesas to provide FlexNoC technology for advanced automotive AI R-Car Gen 5 SoCs, as detailed in a previous collaboration. These developments highlight Arteris’s ongoing engagement with challenges in chip interconnect and integration.
This material may contain third-party opinions, none of the data and information on this webpage constitutes investment advice according to our Disclaimer. While we adhere to strict Editorial Integrity, this post may contain references to products from our partners.
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